1. Field of the Invention
The invention relates to a semiconductor device and method for fabricating the same, and more particularly to an interconnect structure of a semiconductor device and method for fabricating the same.
2. Description of the Related Art
The ever-increasing demand for high-performance semiconductor devices has motivated the semiconductor industry to design and manufacture ultra-large-scale integrated (ULSI) circuits with smaller feature size, higher resolution, denser packaging, and multi-layer interconnects. ULSI technology places stringent demands on global planarity of the interlayer dielectric (ILD) layers. Compared with other planarization techniques, the chemical mechanical polishing (CMP) process produces excellent local and global planarization at low cost. It is thus widely adopted for planarizing inter-level dielectric (silicon dioxide) layers.
FIG. 1 shows a cross section of a conventional semiconductor device 150, and specifically illustrates an interconnect structure. An intermetal dielectric (IMD) layer 112 and an interconnect layer 104 are formed on the interlayer dielectric (ILD) layer 102 and the semiconductor substrate 100. The intermetal dielectric (IMD) layer 112 has a top 122 lower than a metal layer 104. The lower intermetal dielectric (IMD) layer 112 is formed with material loss or recesses by the conventional planarization process. A barrier layer 114 and a poly-plug 116 subsequently formed on the metal layer 104 have residue or short problems if a misalignment problem occurs as shown in FIG. 1. Semiconductor device performance such as yield or reliability thus suffers because the recess problem of the intermetal dielectric (IMD) layer.
Thus, a novel and reliable method of fabricating a semiconductor device with more robust interconnect structure is desirable.